In the strive for making components smaller and smaller in particular for stacking of dies in three dimensions, also the so called through-substrate vias (or through-silicon vias specifically), which are used for routing signals from one side of a substrate to another, are required to be smaller and more densely packed. This will have as a consequence that aspect ratios will be higher, i.e. the ratio between depth and width D/W>5.
The sputtering techniques commonly used for providing metal vias are not feasible for aspect ratios of this magnitude, since they result in non-conformal deposition which in turn causes problems in achieving appropriate “step coverage” on the walls. Technologies that provide better step coverage such as ALD, (MO)CVD and others are expensive, slow and cannot be used for batch processing. The above negative effects are what cause the problems with obtaining appropriate adhesion of barrier and seed layers for plating. Also these technologies most often requires one-sided processing of wafers resulting in a need for complex carrier wafer solutions if the wafers comprise open wafer-through holes.
For high aspect ratio blind via holes there is also a problem when electrodeposition is used in that it is difficult to provide appropriate wetting of the holes and therefore it is difficult to bring the chemistry down into the holes in an appropriate manner.
Also, it is desirable to provide area effective and narrow electrical lead patterns (or routings) on the substrate surface for routing signals to and from components on the substrate through the substrate using the vias. Such routing patterns can be fairly complicated to process and often requires several lithographic steps, and/or CMP (Chemical Mechanical Polishing) which is an expensive procedure. Wet etching of seed layer and barrier layer is quite often complex, if it has to be performed after the Cu electroplating. See e.g. an article by Richard et al, “Barrier and Copper Seed Layer Wet Etching” in Solid State Phenomena, Vol. 103-104, 2005, pp 361-364.
In EP 1 987 535 (Silex) there is disclosed a method of making metal vias using gold. In view of gold being a very expensive material this method is not particularly economically feasible.
Alchimer in WO 2010/133550 discloses a method of making a coated substrate, wherein a cavity is made in a substrate surface by etching. An insulating dielectric layer is deposited on the substrate surface, and then polysilicon, which is in situ doped with phosphorous, is deposited on the dielectric layer. Finally, copper is electrodeposited on the doped polysilicon. No Cu diffusion barrier is provided in this process.
In applicants own WO 2010/059188 A1 simultaneous “self-alignment” of routing and via filling is achieved, but with today available technologies it provides line widths >10 μm, at least in cost effective volume production.